1. Field of the Invention
The present invention relates to a video motion compensation for digital TVs, and more particularly to an apparatus for compensating video motions in digital TVs.
2. Description of the Prior Art
Generally, appliances such as digital TVs, high definition televisions (HDTVs) and moving pictures experts group (MPEG) devices are devices wherein analog video information is converted into a digital signal by a coding and the digital signal is decoded to display the video on a screen.
In cases of televisions adopting the NTSC system, analog video information is sampled at 13.5 MHz. For expressing one sampled digital video information by the unit of 8 bits, it is required to provide a bit rate of 13.5.times.8 Mbps. However, such a video signal of 13.5.times.8 Mbps should be compressed to 6.times.8 Mbps, since television receivers of the NTSC system currently used adopt a sampling frequency of 6 MHz.
Accordingly, in digital TVs, only video information involving motion, from 30 frames scanned per one second is transmitted. That is, pixels involving no motion in one frame are not transmitted and only position vector amount data for moved pixels is transmitted.
As video information Vi corresponding to one frame is inputted, it is converted into the frequency domain, by a discrete cosine transform (DCT) processing. Where one frame is constituted by the same video pixels, it is outputted as one video data. For various video information input, however, it is outputted as a plurality of video data.
A plurality of video data outputted after the DCT are then quantized to a finite number, by a quantization circuit. The quantized video information are encoded into different numbers of bits by a variable length encoder, depending on their generation rates, and then transmitted.
The transmitted video information are decoded into the original video information, according to an inverse quantization and an inverse discrete cosine transform (IDCT) processing achieved by a data decoding device, to be displayed on a screen.
Higher frequencies are required for achieving the above-mentioned encoding and decoding procedures in a real time processing manner.
In HDTVs, a considerably high clock frequency is required for achieving a real time processing, because of a high sampling rate of above 50 MHz. However, such a high frequency has not been realized by existing TTLs and chips of ECL level. Recently, there has been proposed a parallel subframe processing method of dividing video information of one frame into a plurality of subframes and performing encoding and decoding operations for video data of divided sub-frames.
FIG. 1 illustrates a conventional frame division method. As shown in FIG. 1, one frame is divided into a plurality of subframes F1 to FN.
Referring to FIG. 2, there is illustrated a conventional data encoding device. As shown in FIG. 2, the data encoding device comprises a demultiplexor 1 for receiving video information V1 of one frame and dividing it into a plurality of subframes F1 to FN. To the outputs of demultiplexor 1, an encoding circuit 2 is connected, which includes a plurality of encoders. The encoders of the encoding circuit 2 receive and encode video information DM1 to DMn of the subframes 1-N, to compress them, respectively. Compressed video information DE1 to DEn from the encoding circuit 2 are applied to a multiplexor 3 which, in turn, processes them to generate one video information Vo to be transmitted.
FIG. 3 illustrates subframes divided from one frame in accordance with the prior art. As shown in FIG. 3, each of subframes SF1, SF2 is divided into a plurality of basic blocks B to be encoded. Motion-involving pixels of each basic block B are searched and pixels surrounding them are also searched.
Where the basic block B being searched is positioned adjacent to the boundary of the subframe, as indicated by the area Ba in FIG. 3, it is necessary to search even the pixels of basic blocks of a subframe ("SF2" in the case of FIG. 3) positioned adjacent to the subframe ("SF1" in the case of FIG. 3) being searched. For achieving a presumption and a compensation of video motions, it is also necessary to store, in encoders, even subframe portions overlapping with video data of adjacent subframe.
FIG. 4 is a block diagram of a conventional video motion compensating apparatus. As shown in FIG. 4, the motion compensating apparatus comprises a subtraction circuit 10 for receiving video information DMi of subframes of an input frame and video information Hi of subframes of a just previous frame motion-compensated and detecting an error signal indicative of a difference between both the received video information DMi and Mi. To the subtraction circuit 10, a signal coding circuit 20 is connected to receive the error signal from the subtraction circuit 10. The signal coding circuit 20 includes a DCT 21 and a quantization circuit 22, so as to transform and quantize the received error signal to a finite number. The motion compensating apparatus also comprises a variable length encoding circuit 30 connected to the signal coding circuit 20 and adapted to variable length-encode the quantized error signal Qi from the signal coding circuit 20, depending on its generation rate. To the signal coding circuit 20, a signal decoding circuit 40 is also connected, which includes an inverse quantization circuit 41 and an inverse discrete cosine transform circuit IDCT 42. The signal decoding circuit 40 is adapted to receive the error signal Qi from the signal coding circuit 20 and decode it into original error information DQi, through the inverse quantization circuit 41 and the IDCT 42. An adding circuit 50 is connected to the signal decoding circuit 40 and adapted to add the error signal DQi to the video information Mi of the subframes of motion-compensated previous frame which is also received therein. To the adding circuit 50, a subframe storing circuit 60 is connected for storing video information Si outputted from the adding circuit 50. The subframe storing circuit 60 is also adapted to store video information Ii of subframe portions overlapping with surrounding subframes. The motion compensating apparatus also comprises a motion presumption/compensation circuit 70 connected to the subframe storing circuit 60. The motion presumption/compensation circuit 70 is adapted to search positions of moved pixels from video data of the previous frame stored in the subframe storing circuit 60 and the video information of the input frame, calculate positional vector amounts of the moved pixels from data indicative of the searched pixel positions, and compensate the video information of the previous frame by the calculated positional vector amounts. To the subframe storing circuit 60, an interface circuit 80 is connected to send, to the subframe storing circuit 60, video information of basic blocks positioned at each boundary of adjacent subframes.
In the conventional motion compensating apparatus with the above-mentioned construction, the subframe storing circuit 60 receives the video information from the interface circuit 80 and the video information of the subframes of the previous frame. These video data from the subframe storing circuit 60 are sent to the motion presumption/compensation circuit 70, together with the video information of the subframes of the current input frame.
Based on the received video information of the previous and current frames, the motion presumption/compensation circuit 70 searches the positions of moved pixels by basic blocks to detect position data thereof. It also calculates the motion vector amounts of the moved pixels, based on the position data of the detected pixels. The video information of the previous frame are compensated by the calculated motion vector amounts, respectively. Thus, the motion presumption/compensation circuit 70 outputs the compensated video information Mi of the previous frame.
The video information Mi outputted from the motion presumption/compensation circuit 70 is applied to the subtraction circuit 10 which, in turn, generates a difference signal indicative of a difference between the video information Mi and the video information DMi of the current input frame. That is, the subtraction circuit 10 outputs an error signal occurring from the compensated video information.
The error signal outputted from the subtraction circuit 10 is applied to the signal coding circuit 20 in which it is transformed and quantized to a finite number. The modulated error signal is then sent to the variable length encoding circuit 30, so that it has a varied number of bits, depending on its generation rate. The variable length encoding circuit 30 sends the varied error signal to a multiplexor not shown.
On the other hand, the error signal coded in the signal coding circuit 20 is also applied to the signal decoding circuit 40 in which it is converted into the original error signal. The decoded error signal is then sent to the adding circuit 50.
The adding circuit 50 adds the error signal to the motion-compensated video information Mi of the previous frame received from the motion presumption/compensation circuit 70 so that it outputs video information perfectly motion-compensated.
The video information from the adding circuit 50 is sent to the subframe storing circuit 60 and stored again as new reference video information.
Assuming that video information of one frame is divided into N number of subframes to be processed and that the subframes have the same signal amount, a clock frequency for operating each subframe can be reduced to 1/N. That is, the frame division can be achieved without any overlap between adjacent subframes. For individual subframes, simultaneous data coding and decoding can be achieved.
Where the motion presumption and compensation are performed by blocks, all the conventional motion compensating devices mentioned above are required to make blocks positioned at the boundary between adjacent subframes be commonly included in both the adjacent subframes. Video information of the overlapping subframe portions should be also stored. Also, values of signals corresponding to the overlapping subframe portions should be read through the interface circuit, every time when a processing for one frame is completed. As a result, the time taken for the motion compensation is lengthened. Also, there is a difficulty in realizing a simple circuit.